ISO/IEC 14576:1999

Information technology - Synchronous split transfer type system bus (STbus) - Logical layer

This International Standard specifies the logical specifications of STbus which is a high-performance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently. This International Standard is applicable to a high-performance system bus or an I/O bus in a multiprocessor system. Typical STbus applications are a system bus and an I/O bus in a tightly coupled multiprocessor system, and a system bus in a loosely coupled multiprocessor system.

General Information

• Status: Published
• Publication Date: 15-Dec-1999
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Start Date: 29-Feb-2000
• Completion Date: 16-Dec-1999

Standards Content (Sample)

INTERNATIONAL ISO/IEC
STANDARD
14576
First edition
1999-12
Information technology –
Synchronous split transfer type system bus
(STbus) – Logical layer
Technologies de l'information –
Bus de système de transfert de fente synchrone (STbus) –
Couche logique
Reference number
ISO/IEC 14576:1999(E)

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INTERNATIONAL ISO/IEC
STANDARD
14576
First edition
1999-12
Information technology –
Synchronous split transfer type system bus
(STbus) – Logical layer
Technologies de l'information –
Bus de système de transfert de fente synchrone (STbus) –
Couche logique
 ISO/IEC 1999
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– ii – 14576 © ISO/IEC:1999(E)
Contents
1. Overview . 1
1.1 Scope . 1
1.2 Applicability . 1
2. Definitions . 3
2.1 Explanation of Terms . 3
2.2 Notation . 5
3. Interface Specifications . 6
3.1 Interface Signals . 6
4. Bus Operations . 11
4.1 Protocol for Basic Operations . 11
4.2 Transfer Protocol . 16
4.2.1 Bus operation types . 16
4.2.2 Command format . 16
4.2.3 Transfer sequence . 25
4.3 Arbitration . 27
4.4 Status Reports . 27
4.5 Data Transfer . 29
4.5.1 Memory access (write) . 29
4.5.2 Memory access (read) . 35
4.5.3 Control space access (write) . 38
4.5.4 Control space access (read) . 40
4.5.5 Message transfer . 42
4.5.6 Control register access (write) . 44
4.5.7 Control register access (read) . 46
4.6 Lock Operations . 48
4.7 Cache-related Operations . 50
4.7.1 Cache invalidation . 50
4.7.2 Retry indication . 53
4.7.3 Copyback and steal operations after retry indication . 55
4.7.4 Steal inhibit operation . 57
4.8 Error Handling . 59
4.8.1 Handling errors notified in answer . 59
4.8.2 Other error detection . 61

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